? semiconductor components industries, llc, 2003 december, 2003 ? rev. 1 1 publication order number: mld2n06cl/d mld2n06cl preferred device smartdiscretes mosfet 2 amp, 62 volts, logic level n?channel dpak the mld2n06cl is designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontrol unit (mcu). ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high in?rush current or a shorted load condition could occur. this logic level power mosfet features current limiting for short circuit protection, integrated gate?source clamping for esd protection and integral gate?drain clamping for over?voltage protection and sensefet technology for low on?resistance. no additional gate series resistance is required when interfacing to the output of a mcu, but a 40 k w gate pulldown resistor is recommended to avoid a floating gate condition. the internal gate?source and gate?drain clamps allow the device to be applied without use of external transient suppression components. the gate?source clamp protects the mosfet input from electrostatic voltage stress up to 2.0 kv. the gate?drain clamp protects the mosfet drain from the avalanche stress that occurs with inductive loads. their unique design provides voltage clamping that is essentially independent of operating temperature. maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain?to?source voltage v dss clamped vdc drain?to?gate voltage (r gs = 1.0 m w ) v dgr clamped vdc gate?to?source voltage? continuous v gs 10 vdc drain current ? continuous @ t c = 25 c i d self?limited adc total power dissipation @ t c = 25 c p d 40 watts electrostatic voltage esd 2.0 kv operating & storage temperature range t j , t stg ?50 to 150 c thermal characteristics maximum junction temperature t j(max) 150 c thermal resistance ? junction to case ? junction to ambient (note 1.) ? junction to ambient (note 2.) r q jc r q ja r q ja 3.12 100 71.4 c/w maximum lead temperature for soldering purposes, 1/8 from case for 5 sec. t l 260 c 1. when surface mounted to an fr?4 board using the minimum recommended pad size. 2. when surface mounted to an fr?4 board using the 0.5 sq.in. drain pad size. device package shipping 2 ordering information mld2n06cl dpak 75 units/rail case 369c dpak style 2 n?channel marking diagram & pin assignment l2n06cl = device code y = year ww = work week preferred devices are recommended choices for future use and best overall value. d g s r1 r2 http://onsemi.com 1 gate 3 source 2 drain 4 drain 62 v (clamped) 400 m r ds(on) typ 2.0 a i d max v (br)dss 1 2 3 4 yww l2n 06cl 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. MLD2N06CLT4 dpak 2500 tape & reel
mld2n06cl http://onsemi.com 2 drain?to?source avalanche characteristics rating symbol value unit single pulse drain?to?source avalanche energy (starting t j = 25 c, i d = 2.0 a, l = 40 mh) e as 80 mj electrical characteristics (t c = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?to?source breakdown voltage (internally clamped) (i d = 20 madc, v gs = 0 vdc) (i d = 20 madc, v gs = 0 vdc, t j = 150 c) v (br)dss 58 58 62 62 66 66 vdc zero gate voltage drain current (v ds = 40 vdc, v gs = 0 vdc) (v ds = 40 vdc, v gs = 0 vdc, t j = 150 c) i dss ? ? 0.6 6.0 5.0 20 m adc gate?source leakage current (v g = 5.0 vdc, v ds = 0 vdc) (v g = 5.0 vdc, v ds = 0 vdc, t j = 150 c) i gss ? ? 0.5 1.0 5.0 20 m adc on characteristics (note 3.) gate threshold voltage (i d = 250 m adc, v ds = v gs ) (i d = 250 m adc, v ds = v gs , t j = 150 c) v gs(th) 1.0 0.6 1.5 1.0 2.0 1.6 vdc static drain current limit (v gs = 5.0 vdc, v ds = 10 vdc) (v gs = 5.0 vdc, v ds = 10 vdc, t j = 150 c) i d(lim) 3.8 1.6 4.4 2.4 5.2 2.9 adc static drain?to?source on?resistance (i d = 1.0 adc, v gs = 5.0 vdc) (i d = 1.0 adc, v gs = 5.0 vdc, t j = 150 c) r ds(on) ? ? 0.3 0.53 0.4 0.7 ohms forward transconductance (i d = 1.0 adc, v ds = 10 vdc) g fs 1.0 1.4 ? mhos static source?to?drain diode voltage (i s = 1.0 adc, v gs = 0 vdc) v sd ? 1.1 1.5 vdc resistive switching characteristics (note 4.) turn?on delay time t d(on) ? 1.0 1.5 ns rise time (v dd = 30 vdc, i d = 1.0 adc, t r ? 3.0 5.0 turn?off delay time (v dd 30 vdc , i d 1 . 0 adc , v gs(on) = 5.0 vdc, r gs = 25 ohms) t d(off) ? 5.0 8.0 fall time t f ? 3.0 5.0 3. pulse test: pulse width 300 m s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperature. figure 1. output characteristics figure 2. transfer function v ds , drain-to-source voltage (volts) i d , drain current (amps) i d , drain current (amps) v gs , gate-to-source voltage (volts) t j = 25 c v ds 7.5 v t j = 150 c 25 c -55 c 012 3 8 2.5 2.0 1.5 1.0 0.5 0 3.0 3.5 4.0 4567 02 4 68 5 4 3 2 1 0 6.0 v 5.5 v 5.0 v 4.5 v 4.0 v 3.5 v 3.0 v 2.5 v 2.0 v
mld2n06cl http://onsemi.com 3 the smartdiscretes concept from a standard power mosfet process, several active and passive elements can be obtained that provide on?chip protection to the basic power device. such elements require only a small increase in silicon area and/or the addition of one masking layer to the process. the resulting device exhibits significant improvements in ruggedness and reliability as well as system cost reduction. the smartdiscretes device functions can now provide an economical alternative to smart power ics for power applications requiring low on?resistance, high voltage and high current. these devices are designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontroller unit (mcu). ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high in?rush current or a shorted load condition could occur. operation in the current limit mode the amount of time that an unprotected device can withstand the current stress resulting from a shorted load before its maximum junction temperature is exceeded is dependent upon a number of factors that include the amount of heatsinking that is provided, the size or rating of the device, its initial junction temperature, and the supply voltage. without some form of current limiting, a shorted load can raise a device's junction temperature beyond the maximum rated operating temperature in only a few milliseconds. even with no heatsink, the mld2n06cl can withstand a shorted load powered by an automotive battery (10 to 14 volts) for almost a second if its initial operating temperature is under 100 c. for longer periods of operation in the current?limited mode, device heatsinking can extend operation from several seconds to indefinitely depending on the amount of heatsinking provided. short circuit protection and the effect of temperature the on?chip circuitry of the mld2n06cl offers an integrated means of protecting the mosfet component from high in?rush current or a shorted load. as shown in the schematic diagram, the current limiting feature is provided by an npn transistor and integral resistors r1 and r2. r2 senses the current through the mosfet and forward biases the npn transistor's base as the current increases. as the npn turns on, it begins to pull gate drive current through r1, dropping the gate drive voltage across it, and thus lowering the voltage across the gate?to?source of the power mosfet and limiting the current. the current limit is temperature dependent as shown in figure 3, and decreases from about 2.3 amps at 25 c to about 1.3 amps at 150 c. since the mld2n06cl continues to conduct current and dissipate power during a shorted load condition, it is important to provide sufficient heatsinking to limit the device junction temperature to a maximum of 150 c. the metal current sense resistor r2 adds about 0.4 ohms to the power mosfet's on?resistance, but the effect of temperature on the combination is less than on a standard mosfet due to the lower temperature coefficient of r2. the on?resistance variation with temperature for gate voltages of 4 and 5 volts is shown in figure 5. back?to?back polysilicon diodes between gate and source provide esd protection to greater than 2 kv, hbm. this on?chip protection feature eliminates the need for an external zener diode for systems with potentially heavy line transients.
mld2n06cl http://onsemi.com 4 figure 3. i d(lim) variation with temperature figure 4. r ds(on) variation with gate?to?source voltage figure 5. on?resistance variation with temperature figure 6. maximum avalanche energy versus junction temperature figure 7. drain?source sustaining voltage variation with temperature i d(lim) , drain current (amps) t j , junction temperature ( c) v gs = 5 v v ds = 10 v -50 0 50 100 150 5 4 3 2 1 0 6 r ds(on) , on-resistance (ohms) v gs , gate-to-source voltage (volts) i d = 1 a 01 2 3 910 1.0 0.8 0.6 0.4 0.2 0 456 78 t j = -50 c 100 c 25 c r ds(on) , on-resistance (ohms) t j , junction temperature ( c) i d = 1 a -50 50 0 100 150 0.6 0.4 0.3 0.2 0.1 0 0.5 v gs = 4 v v gs = 5 v t j , starting junction temperature ( c) e as , single pulse drain-to-source i d = 2 a 25 50 75 100 125 150 100 80 60 40 20 0 avalanche energy (mj) bv(dss) , drain-to-source sustaining voltage (v) t j = junction temperature -50 0 150 62.5 62.0 61.5 61.0 60.5 60.0 63.0 63.5 64.0 50 100 i d = 20 ma
mld2n06cl http://onsemi.com 5 forward biased safe operating area the fbsoa curves define the maximum drain?to?source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. the curves are based on a case temperature of 25 c and a maximum junction temperature of 150 c. limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. on semiconductor application note, an569, atransient thermal resistance ? general data and its useo provides detailed instructions. maximum dc voltage considerations the maximum drain?to?source voltage that can be continuously applied across the mld2n06cl when it is in current limit is a function of the power that must be dissipated. this power is determined by the maximum current limit at maximum rated operating temperature (1.8 a at 150 c) and not the r ds(on) . the maximum voltage can be calculated by the following equation: v supply = (150 ? t a ) i d(lim) (r q jc + r q ca ) where the value of r q ca is determined by the heatsink that is being used in the application. duty cycle operation when operating in the duty cycle mode, the maximum drain voltage can be increased. the maximum operating temperature is related to the duty cycle (dc) by the following equation: t c = (v ds x i d x dc x r q ca ) + t a the maximum value of v ds applied when operating in a duty cycle mode can be approximated by: v ds = 150 ? t c i d(lim) x dc x r q jc figure 8. maximum rated forward bias safe operating area (mld2n06cl) v ds , drain-to-source voltage (volts) , drain current (amps) v gs = 10 v single pulse t c = 25 c dc 10 ms 100 10 1.0 0.1 0.1 1.0 10 1 ms r ds(on) limit thermal limit package limit i d figure 9. thermal response (mld2n06cl) t, time (s) r(t), normalized effective transient thermal resistance r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 0.01 0.1 1.0 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 d = 0.5 0.02 0.2 0.05 0.1 single pulse 0.01
mld2n06cl http://onsemi.com 6 pulse generator v dd v out v in r gen 50 w z = 50 w 50 w dut r l figure 10. switching test circuit t off output, v out inverted t on t r t d(off) t f t d(on) 90% 90% 10% input, v in 10% 50% 90% 50% pulse width figure 11. switching waveforms active clamping smartdiscretes technology can provide on?chip realization of the popular gate?to?source and gate?to?drain zener d iode clamp elements. until recently, such features have been implemented only with discrete components which consume board space and add system cost. the smartdiscretes technology approach economically melds these features and the power chip with only a slight increase in chip area. in practice, back?to?back diode elements are formed in a polysilicon region monolithicly integrated with, but electrically isolated from, the main device structure. each back?to?back diode element provides a temperature compensated voltage element of about 7.2 volts. as the polysilicon region is formed on top of silicon dioxide, the diode elements are free from direct interaction with the conduction regions of the power device, thus eliminating parasitic electrical effects while maintaining excellent thermal coupling. to achieve high gate?to?drain clamp voltages, several voltage elements are strung together; the mld2n06cl uses 8 such elements. customarily, two voltage elements are used to provide a 14.4 volt gate?to?source voltage clamp. for the mld2n06cl, the integrated gate?to?source voltage elements provide greater than 2.0 kv electrostatic voltage protection. the avalanche voltage of the gate?to?drain voltage clamp is set less than that of the power mosfet device. as soon as the drain?to?source voltage exceeds this avalanche voltage, the resulting gate?to?drain zener current builds a gate voltage across the gate?to?source impedance, turning on the power device which then conducts the current. since virtually all of the current is carried by the power device, the gate?to?drain voltage clamp element may be small in size. this technique of establishing a temperature compensated drain?to?source sustaining voltage (figure 7) effectively removes the possibility of drain?to?source avalanche in the power device. the gate?to?drain voltage clamp technique is particularly useful for snubbing loads where the inductive energy would otherwise avalanche the power device. an improvement in ruggedness of at least four times has been observed when inductive energy is dissipated in the gate?to?drain clamped conduction mode rather than in the more stressful gate?to?source avalanche mode. typical applications: injector driver, solenoids, lamps, relay coils the mld2n06cl has been designed to allow direct interface to the output of a microcontrol unit to control an isolated load. no additional series gate resistance is required, but a 40 k w gate pulldown resistor is recommended to avoid a floating gate condition in the event of an mcu failure. the internal clamps allow the device to be used without any external transistent suppressing components. v dd v bat mld2n06cl g d s mcu
mld2n06cl http://onsemi.com 7 package dimensions dpak case 369c?01 issue o d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h ?t? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.180 0.215 4.57 5.45 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? 123 4 style 2: pin 1. gate 2. drain 3. source 4. drain 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
mld2n06cl http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mld2n06cl/d smartdiscretes and sensefet are trademarks of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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